1. Field of the Invention
The present invention relates to a solid-state image pickup device (image sensor) for use with electronic equipment such as a video camera and a digital still camera and a manufacturing method thereof.
2. Description of the Related Art
A solid-state image pickup device (image sensor) is a semiconductor device having a structure to read out a pixel signal by using a plurality of pixels serving as photoelectric-converting means and a MOS (metal-oxide semiconductor) transistor for selectively reading out signals from the pixels. The solid-state image pickup device is suitable for use with electronic equipment such as a video camera and a digital still camera.
Of the above-mentioned solid-state image pickup device, in particular, a so-called CMOS (complementary MOS) type solid-state image pickup device (CMOS image sensor) manufactured by a CMOS process has merits in which it can be operated at a low voltage, it consumes less electric power, it is multifunction and in which it can be formed as one-chip with peripheral circuits (that is, it can be formed as a SOC (system on-chip)).
Accordingly, the CMOS type solid-state image pickup device receives a remarkable attention as image pickup devices for use as the application to a camera for a mobile phone, a digital still camera and a digital video camera and it is now commercially available on the market.
FIG. 1 of the accompanying drawings is a schematic diagram (diagram showing an arrangement of a circuit) showing an example of an arrangement of a CMOS type solid-state image pickup device (CMOS image sensor) according to the related art.
As shown in FIG. 1, this CMOS image sensor includes a pixel forming region 4 in which a plurality of pixels 1, each of which composed of a photodiode 2 serving as a photoelectric-converting element and a MOS transistor 3 for selectively reading signal electrical charges from the photodiode 2, is arrayed on the same semiconductor substrate in a two-dimensional fashion (that is, an XY matrix fashion) and pixel selection and signal output peripheral circuits 5 and 6 for selecting a pixel and for outputting a signal.
Other regions than the pixel forming region 4, that is, the region containing the pixel selection circuit 5 and the signal output circuit 6 will hereinafter be referred to as a “peripheral circuit forming region”.
In the pixel forming region 4, each pixel 1 consists of the photodiode 2 and three MOS transistors of a transfer transistor 3, a reset transistor 7 and an amplifying transistor 8. Also, in the peripheral circuit forming region, the pixel selection circuit 5 and the signal output circuit 6 are composed of CMOS transistors.
In the CMOS image sensor according to the related art, respective circuits in the peripheral circuit forming region are formed of CMOS transistors.
On the other hand, in the pixel forming region, the MOS transistors constructing the respective pixels are all NMOS (N type MOS) transistors.
It is customary that the NMOS transistor constructing this pixel has the same element isolation structure as that of the NMOS transistor used in the peripheral circuit forming region (see Cited Patent Reference 1, for example).
FIG. 2 is a cross-sectional view showing an element isolation structure for use with the peripheral circuit forming region.
As shown in FIG. 2, an N type semiconductor well region 52 and a P type semiconductor well region 53 are formed within a semiconductor substrate 51. A PMOS (P type MOS) transistor 54 is formed within the N type semiconductor well region 52 and an NMOS transistor 55 is formed within the P type semiconductor well region 53, respectively.
Then, the PMOS transistor 54 and the NMOS transistor 55 are electrically isolated from each other by an element isolation portion 56 formed of a so-called STI (shallow trench isolation) in which an element isolation layer is buried into a groove (trench) formed within the semiconductor substrate 51. This element isolation portion 56 has an oxide film, for example, buried therein as the element isolation layer.
Further, in the CMOS image sensor according to the related art, since the NMOS transistor constructing the pixel is isolated by the element isolation portion having the same structure as that of the NMOS transistor used in the peripheral circuit forming region, the element isolation portion 56 formed of the shallow trench isolation in which the element isolation layer is formed within the semiconductor substrate 51 as shown in FIG. 2 is formed similarly in the pixel forming region 4 shown in FIG. 1 and thereby the pixel forming region 4 is isolated from the adjacent pixel cell 1.
Also, source/drain diffusion layers of transistors such as the transfer transistor 3, the amplifying transistor 8 and the reset transistor 7 formed on each pixel cell 1 of the pixel forming region 4 also are respectively isolated by the element isolation portions 56 having similar arrangements.
[Cited Patent Reference 1]: Official Gazette of Japanese laid-open patent application No. 2003-142674 (FIG. 10)
However, in the related-art CMOS image sensor, as described above, since the element isolation portion 56 is formed by burying the element isolation layer into the trench formed within the semiconductor substrate 51, it is frequently observed that strain and crystal defect occur in the semiconductor substrate 51 due to damages produced when the trench is formed on the semiconductor substrate 51 or stress generated from a difference between coefficients of thermal expansion of the semiconductor substrate 51 and the buried insulating layer (element isolation layer) 56 in the heat treatment process during manufacturing.
Due to the above-mentioned strain and crystal defect, unnecessary electrical charges (leakage electric current and dark electric current) are generated and entered the photodiode 2.
Electrical charges accumulated in the photodiode 2 are transferred through the transfer transistor 3 so that the electrical charge generated due to the strain and the crystal defect becomes noise signals relative to the pixel signal as they are.
Further, since a trench is formed on a single crystal substrate like a silicon substrate, an ending end portion of single crystal is formed not only on the surface of the substrate but also on the side wall of the trench, an interface state density formed at this ending end portion also becomes a factor of the noise signal relative to the image signal.
Also, although the NMOS transistor constructing the pixel is isolated by the element isolation portion 56 having the same structure as that of the NMOS transistor used in the peripheral circuit forming region, there are many examples in which the CMOS transistor for use in the peripheral circuit forming region is manufactured by a forefront process of a microminiaturization technology. Further, since the CMOS transistor is mainly designed for the purpose of increasing an operation speed, decreasing power consumption and saving a space, there are many examples in which a power source voltage also is decreased.
For this reason, if the element isolation portion 56 is optimized in accordance with a design of the CMOS transistor of the peripheral circuit forming region, then it is unavoidable that a solid-state image pickup device will have an arrangement which tends to easily generate the above-mentioned unnecessary electrical charges.